
SC16C850
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NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
25 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, and set the receive FIFO
trigger levels.
7.3.1 FIFO mode
[1]
[2]
[1]
When RXINTLVL, TXINTLVL, FLWCNTL or FLWCNTH contains any value other than 0x00, receive and
Table 10.
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7:6]
Receive trigger level in 32-byte FIFO mode
[1].These bits are used to set the trigger levels for receive FIFO interrupt and flow
control. The SC16C850 will issue a receive ready interrupt when the number of
characters in the receive FIFO reaches the selected trigger level. Refer to
5:4
FCR[5:4]
Transmit trigger level in 32-byte FIFO mode
[2].
These bits are used to set the trigger level for the transmit FIFO interrupt and
flow control. The SC16C850 will issue a transmit empty interrupt when the
number of characters in FIFO drops below the selected trigger level. Refer to
3
FCR[3]
reserved
2
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic. This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO counter
logic. This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default condition)
logic 1 = enable the transmit and receive FIFO
Table 11.
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level (bytes) in 32-byte FIFO mode[1] 00
8
01
16
10
24
11
28